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ASMPT’s Laser Dicing technology enables the Power Semiconductor market to take the next step on their technology roadmap, to lower the costs and increase the productivity and quality of their cutting processes. Our multi-beam laser process to cut through thin (Si/SiC) wafers, will create a ‘Heat Affected Zone’ after the cutting process, due to the modification of the material. This reduces the Die Strength.
To bring a solution for the Power Semiconductor market, ASMPT ALSI created a patented multi beam V-DOE technology for dicing through thin SiC wafers (<150µm). With the modified beam configuration, we can improve the die strength after the cutting process. First, we dice through the material and with a special configuration of our multi-beam, we will clean the sidewalls of the dicing kerf.
The V-DOE concept enables you to:
The Power Semiconductor market is moving towards SiC and GaN wafer substrates. The demand and volume of Power Semiconductor devices is increasing enormously. Therefore, the conventional saw blade dicing technology can no longer be used due to the yield issues like:
Our V-DOE concept results in significant die strength increase with comparable productivity to competitors and blade dicing. As an example, we brought the die strength from the front side of a 60 µm Si MOSFET from 210 Mpa to 1150Mpa. The die strength of the back side improved from 600 Mpa till 1000 Mpa.
Looking at costs, the costs of saw dicing a SiC wafer (100µm) are 14.1 USD per wafer. Dicing with a laser can be done at 8.9 USD per wafer.
This is how our laser technology enables the SiC Technology Roadmap now, and in the future.